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Description
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The Cache/TLB descriptor array intel_ctab[] in cpuid.c and the specification in the Intel manual are different (Software Developer's Manual Volume 2A Instruction Set Reference, A-M Order Number: 253666-026US February 2008). See Table 3-25 from the manual.
The following entries are missing from the intel_ctab[] array:
05H Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
40H No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
48H 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
4EH 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
56H Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
57H Data TLB0: 4 KByte pages, 4-way associative, 16 entries
B1H Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
F0H 64-Byte prefetching
F1H 128-Byte prefetching
The following entries are no longer present in the manual specification:
{ 0x3e, 4, 64, 512*1024, sl2_cache_str}
{ 0x3d, 6, 64, 384*1024, sl2_cache_str}
{ 0x3c, 4, 64, 256*1024, sl2_cache_str}
{ 0x3b, 2, 64, 128*1024, sl2_cache_str}
{ 0x3a, 6, 64, 192*1024, sl2_cache_str}
{ 0x39, 4, 64, 128*1024, sl2_cache_str}
{ 0x73, 8, 0, 64*1024, itrace_str}
None of the entries need to be removed from intel_ctab[]. Though not mentioned in Volume 2A, they are included in the cache descriptor specification in the following document: Intel Processor Identification and the CPUID Instruction Application Note 485 (December 2007 Document Number: 241618-032).
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