The current CMT scheduling infrastructure is capable of load balancing at a single level. Generally, this is done at the chip level...that is, the dispatcher tries to load balance running threads across the system's physical processors.
On single chip, multi-core systems, this same infrastructure is leveraged to load balance at the core/pipeline level (which is currently used on Niagara systems).
Moving forward, where multi-core, multi-chip configurations become prevelant, optimizing at multiple levels becomes desirable (load balancing across both chips, cores, etc).
The RFE seeks to provide an updated dispatcher infrastructure to meet this need, and other needs going forward.