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Description
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As discovered by Juergen Keil:
===============
While my Tecra S1 Pentium-M Centrino notebook is now able to enter S3
suspend-to-ram state, a power-on/resume has always resulted in a full
reboot, not the expected wakeup from S3-STR state.
The 32-bit i386 code at label kernel_wc_code in
usr/src/uts/i86pc/ml/cpr_wakecode.s contains unconditional accesses to
amd specific MSRs - most likely this doesn't work on non-amd cpus:
movl $MSR_AMD_EFER, %ecx / re-enable NX bit
rdmsr
orl $AMD_EFER_NXE, %eax
wrmsr
This should be change to something like
diff -r 111aa1baa84a usr/src/uts/i86pc/ml/cpr_wakecode.s
--- a/usr/src/uts/i86pc/ml/cpr_wakecode.s Mon Oct 29 22:45:33 2007
-0700
+++ b/usr/src/uts/i86pc/ml/cpr_wakecode.s Thu Nov 01 20:37:40 2007
+0100
+
+ testl $X86_NX, x86_feature
+ jz 1f
movl $MSR_AMD_EFER, %ecx / re-enable NX bit
rdmsr
orl $AMD_EFER_NXE, %eax
wrmsr
+1:
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The fix fixed my random reboot caused by resume. My cpu is from the output of
smibios:
Manufacturer: GenuineIntel
Version: Intel(R) Pentium(R) 4 CPU 2.60GHz
Location Tag: WMT478/NWD
Family: 178 (Pentium 4)
CPUID: 0xbfebfbff00000f29
Type: 3 (central processor)
Socket Upgrade: 15 (socket 478)
Socket Status: Populated
Processor Status: 1 (enabled)
Supported Voltages: 1.8V
External Clock Speed: Unknown
Maximum Speed: 3200MHz
Current Speed: 2600MHz
L1 Cache: 5
L2 Cache: 6
L3 Cache: None
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