|
Description
|
While developing Enhanced Speedstep for Solaris, I became aware that our Speedstep
support was not functioning correctly on the Tecra M5 when it was running with dual
core enabled. Our CPU driver indicated that it was unable to retrieve _PSS data from
ACPI for CPU0. This seemed odd since the _PSS was being returned when the M5 was
booted with just a single core enabled.
John Martin provided me with an iasl dump of his M5 booted both with single core
and then with dual core. Sure enough, in the single core case, ssdt_0_A003B.dsl was
returning a _PSS for CPU0. In the dual core case, no _PSS is being returned for either
CPU0 or CPU1. I've looked at the BIOS setup and I don't see where any BIOS setting
should make a difference in this regard (other than the Dynamic CPU Frequency Mode
which was set to Dynamically Switchable in both cases).
I not sure, but I believe that this a BIOS issue that needs to be addressed by Toshiba.
I've attached the iasl dump provided by John Martin
|
