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Description
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Filing this CR under C10 category as starting point, please re-assign if this is not the right categoty.
1. Symptom:
After a Atlas-PEM module was plugging in a St.Paul slot, both the attention(amber) and the power(green) LEDs lit on to indicate a fault condition when the "cfgadm -c connect" command was issued. During the "cfgadm -c connect" command, the St. Paul blade asserted power enable (PWREN_L) and then deasserted it approximately 1.3 secs later.
2. Analysis:
PWRFLT_L from the PEM module is asserted until all internal voltages stabilized. St.Paul stores any power-fault condition in PLX8532 even though PWRFLT_L is de-asserted when MRST_L is de-asserted, i.e., there is no power-fault asserted while PWREN_L is active.
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Work Around
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Tak/Taeon/Jeff,
The changes I created to avoid powering down the PEM on connect will need
to be integrated into Solaris. The contact name for these changes is Govinda Tatti.
He can create an official CR and integrate it in to S11 and S10 Patch release. I can
help with explanations. Here I attach the file changes for s10:
#sccs diffs -C pciehpc.c
------- pciehpc.c -------
*** /tmp/sccs.bgaqPw Thu May 17 11:31:25 2007
--- pciehpc.c Thu May 17 11:31:07 2007
***************
*** 1118,1124 ****
/* 2. set power control to ON */
control = pciehpc_reg_get16(ctrl_p,
ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
! control &= ~PCIE_SLOTCTL_PWR_CONTROL;
pciehpc_issue_hpc_command(ctrl_p, control);
/* 3. wait for DLL State Change event, if it's supported */
--- 1118,1125 ----
/* 2. set power control to ON */
control = pciehpc_reg_get16(ctrl_p,
ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
! control &= ~PCIE_SLOTCTL_PWR_CONTROL; /* enable power */
! control &= ~PCIE_SLOTCTL_PWR_FAULT_EN; /* disable power fault */
pciehpc_issue_hpc_command(ctrl_p, control);
/* 3. wait for DLL State Change event, if it's supported */
***************
*** 1159,1164 ****
--- 1160,1173 ----
goto cleanup1;
}
+ /* reset power fault interrupt */
+ status = pciehpc_reg_get16(ctrl_p,
+ ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS);
+ status |= PCIE_SLOTSTS_PWR_FAULT_DETECTED;
+ pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS,
+ status);
+ delay(drv_usectohz(100000));
+
/* enable power fault detection interrupt */
control |= PCIE_SLOTCTL_PWR_FAULT_EN;
pciehpc_issue_hpc_command(ctrl_p, control);
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