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Work Around
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Following patch should fix the comments:
--- usr/src/uts/i86pc/io/agpgart/agptarget.c Sa Sep 10 01:44:51 2005
+++ current/src/uts/i86pc/io/agpgart/agptarget.c Di Sep 13 19:43:40 2005
@@ -28,7 +28,7 @@
dev_info_t *tsoft_dip;
ddi_acc_handle_t tsoft_pcihdl;
uint32_t tsoft_devid;
- off_t tsoft_acaptr; /* offset of ACAPID register */
+ off_t tsoft_acaptr; /* The offset of the ACAPID register */
kmutex_t tsoft_lock;
}agp_target_softstate_t;
@@ -38,7 +38,7 @@
ddi_get_soft_state(agptarget_glob_soft_handle, instance));
/*
- * AMD8151 bridge is the only 64 bit hardware supported
+ * The AMD8151 bridge is the only supported 64 bit hardware
*/
static int
is_64bit_aper(agp_target_softstate_t *softstate)
@@ -50,10 +50,10 @@
* agp_target_cap_find()
*
* Description:
- * This function seach the linked capability list to find the
- * offset of AGP capability register. When not found, return 0.
+ * This function searches the linked capability list to find the
+ * offset of the AGP capability register. When it was not found, return 0.
* This works for standard AGP chipsets, but not for some Intel chipsets,
- * like I830M/I830MP/I852PM/I852GME/I855GME. It will return 0 for
+ * like the I830M/I830MP/I852PM/I852GME/I855GME. It will return 0 for
* these chipsets even if AGP is supported. So the offset of acapid
* should be set manually in thoses cases.
*
@@ -62,7 +62,7 @@
*
* Returns:
* 0 No capability pointer register found
- * nexcap AGP capability pointer register offset
+ * nexcap The AGP capability pointer register offset
*/
static off_t
agp_target_cap_find(ddi_acc_handle_t pci_handle)
@@ -71,7 +71,7 @@
uint32_t ncapid = 0;
uint8_t value = 0;
- /* Check if this device supports capibility pointer */
+ /* Check if this device supports the capability pointer */
value = (uint8_t)(pci_config_get16(pci_handle, PCI_CONF_STAT)
& PCI_CONF_CAP_MASK);
@@ -80,15 +80,15 @@
/* Get the offset of the first capability pointer from CAPPTR */
nextcap = (off_t)(pci_config_get8(pci_handle, AGP_CONF_CAPPTR));
- /* Check AGP capability from the first capability pointer */
+ /* Check the AGP capability from the first capability pointer */
while (nextcap) {
ncapid = pci_config_get32(pci_handle, nextcap);
/*
- * AGP3.0 rev1.0 127 capid assigned by PCI SIG,
+ * AGP3.0 rev1.0 127 the capid was assigned by the PCI SIG,
* 845 data sheet page 69
*/
if ((ncapid & PCI_CONF_CAPID_MASK) ==
- AGP_CAP_ID) /* AGP cap found */
+ AGP_CAP_ID) /* The AGP cap was found */
break;
nextcap = (off_t)((ncapid & PCI_CONF_NCAPID_MASK) >> 8);
@@ -102,8 +102,8 @@
* agp_target_get_aperbase()
*
* Description:
- * This function get the AGP aperture base address from agp target
- * register, the AGP aperture base register programmed by BIOS.
+ * This function gets the AGP aperture base address from the AGP target
+ * register, the AGP aperture base register was programmed by the BIOS.
*
* Arguments:
* softstate driver soft state pointer
@@ -112,8 +112,8 @@
* aper_base AGP aperture base address
*
* Notes:
- * If 64bit bridge deice available, the agp aperture base address
- * can be 64 bit
+ * If a 64bit bridge device is available, the AGP aperture base address
+ * can be 64 bit.
*/
static uint64_t
agp_target_get_apbase(agp_target_softstate_t *softstate)
@@ -139,14 +139,14 @@
* agp_target_get_apsize()
*
* Description:
- * This function get the agp aperture size by read the agp aperture
+ * This function gets the AGP aperture size by reading the AGP aperture
* size register.
* Arguments:
* softstate driver soft state pointer
*
* Return:
- * size agp aperture size in megabytes
- * 0 unexpected error
+ * size The AGP aperture size in megabytes
+ * 0 an unexpected error
*/
static size_t
agp_target_get_apsize(agp_target_softstate_t *softstate)
@@ -159,7 +159,7 @@
cap = softstate->tsoft_acaptr;
if ((softstate->tsoft_devid & VENDOR_ID_MASK) == INTEL_VENDOR_ID) {
- /* extend this value to 16 bit for later test */
+ /* extend this value to 16 bit for later tests */
value = (uint16_t)pci_config_get8(softstate->tsoft_pcihdl,
cap + AGP_CONF_APERSIZE) | AGP_APER_SIZE_MASK;
} else {
@@ -213,8 +213,8 @@
}
/*
* In some cases, there is no APSIZE register, so the size value
- * of 256M could be wrong. Check the value by reading
- * the size of the first register set in PCI configuration space.
+ * of 256M could be wrong. Check the value by reading the size of
+ * the first register which was set in the PCI configuration space.
*/
if (size == 256) {
if (ddi_dev_regsize(softstate->tsoft_dip,
@@ -238,7 +238,7 @@
{
ASSERT(softstate->tsoft_acaptr);
- /* Disable GTLB for Intel chipsets */
+ /* Disable the GTLB for Intel chipsets */
pci_config_put16(softstate->tsoft_pcihdl,
softstate->tsoft_acaptr + AGP_CONF_CONTROL, 0x0000);
@@ -267,7 +267,7 @@
kbytes = 1024; /* 1024K preallocated memory */
break;
default:
- kbytes = 0; /* unexpected case */
+ kbytes = 0; /* an unexpected case */
}
break;
case INTEL_BR_830M:
@@ -284,7 +284,7 @@
kbytes = 8 * 1024; /* 8M preallocated memory */
break;
default:
- kbytes = 0; /* unexpected case */
+ kbytes = 0; /* an unexpected case */
}
break;
case INTEL_BR_855GM:
@@ -306,7 +306,7 @@
kbytes = 32 * 1024; /* 32M preallocated memory */
break;
default:
- kbytes = 0; /* unexpected case */
+ kbytes = 0; /* an unexpected case */
}
break;
case INTEL_BR_865:
@@ -322,7 +322,7 @@
kbytes = 16 * 1024; /* 16M preallocated memory */
break;
default:
- kbytes = 0; /* unexpected case */
+ kbytes = 0; /* an unexpected case */
}
break;
default:
@@ -395,7 +395,7 @@
PCI_CONF_VENID);
softstate->tsoft_acaptr = agp_target_cap_find(softstate->tsoft_pcihdl);
if (softstate->tsoft_acaptr == 0) {
- /* Make correction for some Intel chipsets */
+ /* Make a correction for some Intel chipsets */
if ((softstate->tsoft_devid & VENDOR_ID_MASK) ==
INTEL_VENDOR_ID)
softstate->tsoft_acaptr = AGP_CAP_OFF_DEF;
@@ -524,11 +524,11 @@
}
/*
- * This ioctl is only for intel agp chipsets.
- * It is not nessary for AMD8151 AGP bridge, because
- * this register in AMD8151 does not control any hadware.
- * It is only provided for compatible with intel agp bridge
- * Please refer to <<AMD8151 data sheet>> page 24,
+ * This ioctl is only for Intel AGP chipsets.
+ * It is not necessary for the AMD8151 AGP bridge, because
+ * this register in the AMD8151 does not control any hadware.
+ * It is only provided for compatibility with an Intel AGP bridge.
+ * Please refer to the <<AMD8151 data sheet>> page 24,
* AGP device GART pointer.
*/
case AGP_TARGET_SET_GATTADDR:
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